Methods and apparatus for configuring and reconfiguring a partial reconfiguration region

ABSTRACT

An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

This application is a continuation of U.S. patent application Ser. No.14/723,876, filed May 28, 2015, which is hereby incorporated byreference herein in its entirety. This application claims the benefit ofand claims priority to U.S. patent application Ser. No. 14/723,876,filed May 28, 2015.

BACKGROUND

Reconfigurable integrated circuit devices, such as programmable logicdevices (PLDs), are often included in complex embedded systems. A PLD istypically composed of a number of logic elements, sometimes referred toas logic array blocks (LABs) or configurable logic blocks (CLBs), whichare sometimes referred to as logic elements. Such logic elements mayinclude a look-up table (LUT) or product term, carry-out chain,register, and other elements. Multiple logic elements or LABs may beconnected to horizontal and vertical conductors that may extend thelength of the PLD's core logic region and connect to input-output (IO)and peripheral blocks.

With increasing device capacity and complexity, partial reconfigurationhas become an important feature in PLDs. Such feature is driven by theneed to shorten the configuration time to more quickly bring up a PLD,as well as the need to reconfigure the PLD on the fly to reduce oreliminate system downtime. Generally, a PLD configuration may includecore logic configuration and IO configuration. Generally, IOconfiguration is different from core logic configuration, due to thevariance in configuration elements and structures. For example, IOconfiguration may include a group of serially-connected configurationshift registers (collectively referred to as a configuration shiftregister chain). However, the configuration shift registers can only befully configured in a regular full device configuration orreconfiguration (e.g., configured in the same way as the core logicregion of the PLD). Reconfiguring any part of the configuration shiftregisters may thus require the PLD to be powered down (or otherwisedeactivated or suspended). As a result, the configuration of the PLD mayneed to be restarted from the beginning each time, which is laboriousand time-consuming.

SUMMARY

In accordance with the present invention, apparatuses and methods areprovided for configuring and reconfiguring a partial reconfigurationregion of an integrated circuit.

It is appreciated that the present invention can be implemented innumerous ways, such as a process, an apparatus, a system, or a device.Several inventive embodiments of the present invention are describedbelow.

An integrated circuit is disclosed. The integrated circuit includes agroup of configuration registers that are connected serially to form aconfiguration shift register (CSR). A group of CSRs may be partitionedinto a predetermined number of CSR partial reconfiguration regions, witheach CSR partial reconfiguration region being connected to a partialreconfiguration (PR) circuit. Each PR circuit includes region enablecircuitry and region control circuitry. The region enable circuitry mayreceive PR circuit enable data and selectively enable reconfiguration ofthe CSR partial reconfiguration region connected to the PR circuit basedon the PR circuit enable data. Accordingly, the region control circuitrymay receive global configuration control signals and generate localreconfiguration control signals that selectively enable CSR data whenthe reconfiguration of the CSR partial reconfiguration region is enabledby the region enable circuitry. The generated local reconfigurationcontrol signals may be used to selectively enable CSR data to be writteninto the CSR partial reconfiguration region when the reconfiguration ofthe CSR partial reconfiguration region is enabled.

A method of configuring an integrated circuit is also disclosed. Themethod includes receiving an input-output (IO) signal with aconfiguration shift register (CSR) partial reconfiguration region. Priorto receiving the IO signal, configuration data is received using apartial reconfiguration (PR) circuit to determine a state of the CSRpartial reconfiguration region based on the configuration data. Thestate of the CSR partial reconfiguration region is determined bydetermining whether a configuration data portion of the PR region ispresent in the configuration data. Subsequently, the PR circuit mayselectively enable a signal shifting function that uses the IO signalbased on the state of the partial reconfiguration circuit. The signalshifting function selectively enables the CSR partial reconfigurationregion.

A method of reconfiguring a configuration shift register (CSR) partialreconfiguration region of an integrated circuit is disclosed. The methodincludes receiving configuration data with a partial reconfiguration (PRcircuit) that is connected to the CSR partial reconfiguration region.The PR circuit may receive global configuration control signals. The PRcircuit may determine whether the CSR partial reconfiguration circuit isenabled by determining whether a configuration data portion of the CSRpartial reconfiguration region is present in the input configurationdata. When the configuration data portion of the partial reconfigurationcircuit is present in the configuration data, the PR circuit maygenerate local reconfiguration control signals based on theconfiguration data portion to facilitate the reconfiguration of the CSRpartial reconfiguration region.

Further features of the invention, its nature and various advantages,will be more apparent from the accompanying drawings and the followingdetailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an illustrative programmable integrated circuitin accordance with an embodiment of the present invention.

FIG. 2 is a block diagram of an illustrative computer equipment that maybe used to implement computer-based software tools in accordance with anembodiment of the present invention.

FIG. 3 is an illustrative integrated circuit having a configurationshift register chain in accordance with an embodiment of the presentinvention.

FIG. 4 is an illustrated circuit diagram of a partial reconfigurationcircuit coupled to a partial reconfiguration region in accordance withan embodiment of the present invention.

FIG. 5 shows illustrative bitstream format for a configuration bitstreamthat can be loaded into a programmable integrated circuit in accordancewith an embodiment of the present invention.

FIG. 6 shows another illustrative configuration bitstream format inaccordance with an embodiment of the present invention.

FIG. 7 is an illustrative timing diagram showing the outputs of full andinitial partial configuration shift register (CSR) configurations of apartial reconfiguration circuit in accordance with an embodiment of thepresent invention.

FIG. 8 is an illustrative timing diagram showing the outputs of partialconfiguration shift register (CSR) reconfiguration of a partialreconfiguration circuit in accordance with an embodiment of the presentinvention.

FIG. 9 is a flow chart of illustrative steps for reconfiguring a partialreconfiguration circuit in accordance with an embodiment of the presentinvention.

DETAILED DESCRIPTION

The embodiments provided herein include integrated circuit structuresand methods for configuring and reconfiguring a partial reconfigurationregion of an integrated circuit.

It will be obvious, however, to one skilled in the art, that the presentexemplary embodiments may be practiced without some or all of thesespecific details. In other instances, well-known operations have notbeen described in detail in order not to obscure unnecessarily thepresent embodiments.

FIG. 1 is a diagram of an illustrative integrated circuit 10 inaccordance with an embodiment of the present invention. Integratedcircuit 10 has input-output (IO) circuitry 12 for driving signals off ofintegrated circuit 10 and for receiving signals from other circuits ordevices via IO pins 14. Interconnection resources 16 such as global andlocal vertical and horizontal conductive lines and busses may be used toroute signals on integrated circuit 10. Interconnection resources 16include fixed interconnects (conductive lines) and programmableinterconnects (e.g., programmable connections between respective fixedinterconnects). The programmable interconnects associated withinterconnection resources 16 may be considered to be a part ofprogrammable logic regions 18.

Memory elements 20 may be formed using complementarymetal-oxide-semiconductor (CMOS) integrated circuit technology (as anexample). In the context of programmable logic device, memory elements20 may store configuration data and are therefore sometimes referred toas configuration random-access memory (CRAM) cells. In general,configuration random-access memory elements 20 may be arranged in anarray pattern. In a programmable logic device, there may be millions ofmemory elements 20 on a single device. A user (e.g., a logic designer)may provide configuration data for the array of memory elements duringprogramming operation. Once loaded with configuration data, memoryelements 20 may selectively control (e.g., turn on and off) portions ofthe circuitry in programmable logic regions 18 and thereby customize itsfunctions as desired.

The circuitry of integrated circuit 10 may be organized using anysuitable architecture. For example, programmable logic regions 18 may beorganized in a series of rows and columns of larger programmable logicregions each of which contains multiple smaller regions. The largerregions are sometimes referred to as logic array blocks. The smallerlogic regions are sometimes referred to as logic elements. A typicallogic element may contain a look-up table, registers, and programmablemultiplexers. If desired, programmable logic regions 18 may be arrangedin more levels or layers in which multiple large regions areinterconnected to form still larger portions of logic.

Horizontal and vertical conductors and associated control circuitry maybe used to access memory elements 20 when memory elements 20 arearranged in an array. The control circuitry, for example, may be used toclear all or some of the memory elements. The control circuitry may alsowrite data to memory elements 20 and may read data from memory elements20. Memory elements 20 may be loaded with configuration data, forinstance, in CRAM arrays. The loaded configuration data may then be readout from the memory array to confirm proper data capture beforeintegrated circuit 10 is used during normal operation in a system.

In addition to the relatively large blocks of programmable logic regionsthat are shown in FIG. 1, integrated circuit 10 generally also includessome programmable logic components associated with IO circuitry 12 onintegrated circuit 10. For example, IO circuitry 12 may containserially-coupled configuration shift registers (CSRs), which arecollectively referred to as a CSR chain, for carrying out IO andperipheral operations control in integrated circuit 10 based on receivedIO configuration information. However, the CSR chain can only be fullyconfigured in a regular full configuration or reconfiguration (e.g.,configured in the same way as the core logic region of integratedcircuit 10). Reconfiguring any part of the CSR chain requires integratedcircuit 10 to be powered down (or otherwise deactivated or placed in asuspended state). As a result, the configuration of integrated circuit10 needs to be restarted from the beginning each time, which islaborious and time-consuming.

A flexible CSR configuration mechanism is required to perform circuitoperations that support both full and partial CSR configurations duringboth device configuration and reconfiguration and in user mode (e.g.,during normal operation). Such a mechanism may shorten the configurationtime for the integrated circuit, as well as provide the ability toreconfigure the IO and peripheral blocks of the integrated circuit onthe fly to reduce or eliminate system down time. With the flexible CSRconfiguration mechanism, a CSR chain may be partitioned into a group ofshift register partial reconfiguration (PR) regions (which will bereferred to as PR regions hereafter). A PR region may include aconfiguration shift register (e.g., a segment of two or more connectedregister circuits) that is serially-coupled to another configurationshift register in the next PR region in the group. Once the integratedcircuit is configured, the flexible configuration mechanism, which willbe described in detail below, is put into place to determine whether anyof the PR regions is enabled or disabled.

In a typical design flow, a circuit designer would use electronic designautomation (EDA) tool to create a circuit design, and the EDA tool wouldgenerate configuration data (e.g., configuration bitstream) that maythen be used to configure an integrated circuit. FIG. 2 is anillustrative computer equipment that can be used for this purpose. Asshown in FIG. 2, computer equipment 256 may include processing circuitry260. Computer equipment 256 may be based on one or more processors suchas personal computers, workstations, etc. Processing circuitry 260 mayinclude circuitry for performing various supported instructions. Storage254 in processing circuitry 260 may be organized to form shared andstand-alone databases. The stored information in the storage 254 mayinclude input and output data 255. For example, input data may includesettings selected by a user or a software library. Output data mayinclude modeling results, configuration data, reports and any othersuitable processed output from computer equipment 256.

In supporting design operations involved in implementing a desiredcustom logic function, computer equipment 256 may use software that runson processing circuitry 260. This software may take the form of one ormore programs. For example, the software is an EDA tool. When theprograms are running on computer equipment 256, computer equipment 256is sometimes referred to as a computer-aided design tool (or tools).

Input and output devices 257 may include input devices such as pointingdevices and keyboards and may include output devices such as printersand displays. As shown in FIG. 2, computer equipment 256 may displayon-screen options 259 on a display. The user may click on theseon-screen options or may otherwise make selections based on thedisplayed information. The user may also provide input by typing intotext boxes, by performing drag and drop operations, using tabs, etc.Input and output data 261 may include input data (e.g., data that a userhas typed into a text-box or has selected using a drop-down menu orother selectable options) and output data (e.g., modeling results,reports, information indicative of design choices, etc.). Input andoutput data 261 may be displayed on a display or printed for the user.

Communication circuitry 262 may facilitate data and information exchangebetween various circuits of computer equipment 256 through bus interfacecircuitry 250. As an example, communication circuitry 262 may providevarious protocol functionality (e.g., Transmission ControlProtocol/Internet Protocol (TCP/IP) (including the physical layer, orPHY), User Datagram Protocol (UDP) etc.), as desired. As anotherexample, communication circuitry 262 may communicate with network 263(e.g., Ethernet, token ring, etc.). Network 263 may include one or moreservers 264 that store data and information. During integrated circuittesting, communication circuitry 262 may be configured to storeperformance results of each tested integrated circuit on server 264. Ifdesired, communication circuitry 262 may be used to send and receivedata such as the performance results from server 264 over network 263.

FIG. 3 is an illustrative integrated circuit 300 having a configurationshift register (CSR) chain 308, in accordance with an embodiment of thepresent invention. Integrated circuit 300 includes core logic region 303and CSR chain 308. CSR chain 308 may include of one or more CSRs, witheach CSR containing a group of serially-coupled configuration registers335. As shown in FIG. 3, CSR chain 308 is coupled to a group ofinput-output (IO) circuits (e.g., IO blocks 304A and 304B) that isformed within IO and periphery region 305 of integrated circuit 300. CSRchain 308 is configured to control IO blocks 304A and 304B to carry outIO and peripheral functions (or operations).

In one embodiment, CSR chain 308 may be fully or partially configured(or reconfigured) in a device configuration phase or in user mode. To doso, CSR chain 308 may be partitioned (or segmented) into a predeterminednumber of CSR partial reconfiguration regions (which may be referred toas PR regions herein) for individual PR region enabling. For example,CSR chain 308 may be partitioned into two PR regions 321A and 321B. Amultiplexer (e.g., multiplexer 307) is added to the end of each PRregion so as to allow one PR region (e.g., PR region 321A) to beconnected to the next PR region (e.g., PR region 321B), or to beskipped. In one embodiment, each of the partitioned PR regions (e.g., PRregions 321A and 321B) may be coupled to a partial reconfiguration (PR)circuit for individual PR region configuration. For example, PR region321A is coupled to PR circuit 302A, and PR region 321B is coupled to PRcircuit 302B. In one embodiment, a PR circuit may include region enablecircuitry 351 and region control circuitry 352. As shown in FIG. 3,region enable circuitry 351 is arranged in parallel with CSR chain 308.Region enable circuitry 351 is added to the PR region serial connectionpath to form an enable shift register (ESR) chain 356 for eachindividual PR region enabling. A more detailed description of PR region321A and PR circuit 302A are provided later with reference to FIG. 4.

In one embodiment, PR circuits 302A and 302B may form a flexible CSRconfiguration mechanism that supports both full and partial CSRconfigurations in both device configuration (or reconfiguration) phaseand user mode through a general configuration controller (e.g., controlcircuit 301). External configuration data (bitstream) may be provided tocontrol circuit 301 in integrated circuit 300 through a programmingmeans, which is not shown in FIG. 3. Configuration signals (e.g., inputCSR signal DIN 311, clock signal CLK 312, CSR clock enable signal CSR_CE315, CSR done signal CSR_Done 316, global freeze signal Global_Freeze314, PR circuit enable data signal Region_En_In 318, PR circuit clockenable signal Region_CE 317) can be generated by control circuit 301.Control circuit 301 can also receive the configuration signals from corelogic region 303 via control path 361 to allow the configuration (orreconfiguration) of CSR chain 308 to be driven by core logic region 303.

By way of example, the flexible CSR configuration mechanism may beconfigured to support both full and partial CSR configuration in bothdevice configuration (or reconfiguration) phase and user mode in thefollowing manner. First, Global_Freeze 314 is asserted to globallyisolate IO blocks 304A and 304B (each under the control of CSR 308) fromcore logic region 303. It should be noted that this step only occurs ina full CSR configuration or reconfiguration operation. When Region_CE317 is asserted, CLK 312 is enabled and Region_En_In 318 is shifted into enable PR regions 321A and 321B. This step defines the actual CSRchain for the CSR configuration (or reconfiguration), and enables PRregions 321A and 321B to be configured. Once the shifting operation iscompleted, Region_CE 317 is deasserted to apply the shifted Region_En_In318 to region control circuitry 352 of each PR circuit 302A and 302B. Inthis scenario, each of PR regions 321A and 321B may be locally frozen(e.g., isolated) by region control circuitry 352 to facilitate the CSRconfiguration.

During the CSR configuration, CSR_Done 316 is deasserted to indicate thestart of the CSR configuration. When CSR_CE 315 is asserted, CLK 312 isenabled and configuration data DIN 311 is shifted in. This step drivesthe configuration data into the defined (or enabled) PR regions 321A and321B. Once the shifting operation is completed, CSR_CE 315 is deassertedand CSR_Done 316 is asserted to apply the shifted DIN 311 to IO blocks304A and 304B to be controlled. To release the previously enabled PRregions 321A and 321B from local freeze, Region_CE 317 is asserted toenable CLK 312 and shift in Region_En_In 318 to disable PR regions 321Aand 321B. Once the shifting operation is completed, Region_CE 317 isdeasserted to apply the shifted Region_En_In 318 to PR regions 321A and321B to release them from local freeze. Subsequently, Global_Freeze 314is deasserted to release IO blocks 304A and 304B from being controlledby the CSR configuration. It should be noted that this step may onlyoccur after the full CSR configuration or reconfiguration operation isdone.

FIG. 4 shows an illustrative circuit diagram of one embodiment of PRcircuit 302A coupled to PR region 321A. As described above, PR circuit302A may include region enable circuitry 351 and region controlcircuitry 352. In an exemplary embodiment, region enable circuitry 351may include an enable register (e.g., enable register 420A) having anoutput coupled to a shadow enable register (e.g., shadow enable register420B). These enable registers of PR region 321A are serially connectedto enable registers of a next PR region to form an enable shift register(ESR) chain (e.g., ESR chain 356 of FIG. 3), which may be driven bycontrol circuit 301 of FIG. 3 with a separate clock enable signal,Region_CE 317.

In one embodiment, region enable circuitry 351 may receive ESR data(also referred to as PR circuit enable data) such as Region_En_In 318 asan input and selectively enable reconfiguration of PR region 321A, basedon the ESR data. For example, when Region_CE 317 is asserted, clocksignal CLK 312 is enabled and enable register 420A of region enablecircuitry 351 is supplied with Region_En_In 318 that enables thereconfiguration of PR region 321A. In this configuration, Region_En_In318 may shift out of enable register 420A as region enable circuitryoutput 423. In one embodiment, region enable circuitry output 423 may betransmitted out as input PR circuit enable data for the next PR region(e.g., PR region 321B of FIG. 3) for the same purpose of enabling thereconfiguration of the next PR region. A copy of region enable circuitryoutput 423 is transferred to shadow enable register 420B so that onlythe configuration data associated with PR region 321A is stored. Theshift operation of shadow enable register 420B is clocked by CLK 312 andan active high control signal (e.g., control signal 461) that producedby inverter 422 when Region_CE 317 is deasserted. As a result, a regionenable circuitry output (e.g., Region_En 411) is shifted out of shadowenable register 420B in synchronization with CLK 312.

The resulting Region_En 411 is supplied to region control circuitry 352.In an exemplary embodiment, region control circuitry 352 may includethree logic gates (e.g., logic gates 424, 425, and 426). Each logic gateis configured to receive a corresponding global configuration controlsignal (e.g., Global_Freeze 314, CSR_CE 315, and CSR_Done 316) andRegion_En 411 to produce local reconfiguration control signal (e.g.,Region_CSR_CE 415, Region_Done 416, and Region_Freeze 414). These localreconfiguration control signals may collectively function to performregion enabling operations that control the configuration operation ofPR region 321A. For example, the region enabling operations include, butnot limited to, locally freezing (e.g., isolating) PR region 321A fromIO block 304A, enabling a shifting operation of the enabled PR region321A, and controlling multiplexer 307 to select either DIN 311 or ashifted version of DIN 311 from PR region 321A to be transmitted to thenext PR region for configuration.

As described above, PR region 321A may be part of a group of connectingCSR partial reconfiguration regions that forms CSR chain 308 of FIG. 3.Referring to FIG. 4, PR region 321A may include multiple configurationregisters (e.g., configuration registers 435A, 435B, and 435C) that areconnected as a shift register. For example, when PR region 321A isenabled for CSR configuration, CSR data input (e.g., DIN 311) will beloaded onto configuration registers 435A, 435B, and 435C. In oneembodiment, configuration registers 435A, 435B, and 435C are clocked byRegion_CSR_CE 415 and CLK 312 and provide shifted data bit outputs tothe corresponding logic gates (e.g., logic gate 436A, 436B and 436C).These logic gates are controlled by Region_Done 416 to configure IOblock 304A.

Once the shifting operation is complete, a shifted data output of DIN311 is provided to an input of multiplexer circuit 307. The other inputof multiplexer circuit 307 is driven by DIN 311. The select input ofmultiplexer circuit 307 is controlled by Region_En 411 of region enablecircuit 351. In one embodiment, multiplexer circuit 307 may operativelycouple to PR region 321A to allow the output of PR region 321A to betransmitted to the next PR region as an input data signal. In anotherembodiment, multiplexer circuit 307 may operatively couple to PR region321A to allow DIN 311 to bypass (e.g., skip) PR region 321A when PRregion 321A is disabled from CSR configuration. For example, when PRregion 321A is enabled, multiplexer circuit 307 may select the shifteddata output of DIN 311 based on Region_En 411. In another example, whenPR region 321A is disabled, multiplexer circuit 307 may select DIN 311instead.

In one embodiment, PR circuit 302A and PR region 321A may collectivelyform a flexible CSR configuration mechanism that facilitates IOconfiguration. Such a mechanism can be used to implement different CSRconfigurations (e.g., full CSR configuration (or reconfiguration),initial partial CSR configuration, and partial CSR reconfiguration). Inan exemplary embodiment shown in FIG. 4, during a device configuration(or reconfiguration) phase, PR region 321A and all other PR regions(e.g., PR region 321B) in the same CSR chain (e.g., CSR chain 308 ofFIG. 3), are enabled to perform the full CSR configuration (orreconfiguration) operation. To do so, a global freeze signal (e.g.,Global_Freeze 314) is asserted (e.g., via control circuit 301 of FIG. 3)to globally isolate all the PR regions in the CSR chain. Following that,PR circuit enable data (e.g., Region_En_In 318) is shifted into theintegrated circuit through region enable circuitry 351 to enable theconfiguration (or reconfiguration) of all the PR regions. An output(e.g., Region_En 411) from region enable circuitry 351 will be generatedand applied to region control circuitry 352 to generate thecorresponding local configuration (or reconfiguration) control signals(e.g., Region_CSR_CE 415, Region_Done 416, and Region_Freeze 414) toconfigure the PR regions. Once the configuration operation is complete,the ESR data is shifted into the integrated circuit again to disable thePR regions.

The initial partial CSR configuration may have similar circuitoperations with the full CSR configuration with the exception that theinitial partial CSR configuration enables the initial functionality ofspecific PR regions of the integrated circuit. In an exemplaryembodiment shown in FIG. 4, during a device configuration phase, thespecific PR regions (e.g., PR region 321A) may be enabled to perform theinitial partial CSR configuration operation. Other PR regions (e.g., PRregion 321B) in CSR chain 308 will be disabled (e.g., not configured).In other words, the flexible CSR mechanism in each of the disabled PRregions will not be activated for individual PR region enabling. To doso, global freeze signal (e.g., Global_Freeze 314) is asserted (e.g.,via control circuit 301 of FIG. 3) to globally isolate all the PRregions in the CSR chain from a core logic region (e.g., core logicregion 303 of FIG. 3) of the integrated circuit. Following that,Region_En_In 318 is shifted into the integrated circuit through regionenable circuitry 351 to enable only the configuration of the enabled PRregion 321A. An output (e.g., Region_En 411) from region enablecircuitry 351 will be generated and applied to region control circuitry352 to generate the corresponding local configuration control signals(e.g., Region_CSR_CE 415, Region_Done 416, and Region_Freeze 414) toconfigure the PR region 321A. Once the configuration operation iscomplete, the ESR data is shifted into the integrated circuit again todisable the enabled PR region 321A.

Partial CSR reconfiguration can be initiated to achieve IOreconfiguration in the integrated circuit during user mode. A user(e.g., a logic designer) may provide new configuration data, which willbe described in detailed in FIGS. 5 and 6, that defines one or more PRregions to be reconfigured during the partial CSR reconfigurationoperation. In this scenario, only the PR regions defined in the newconfiguration data will be locally “frozen” (e.g., logically isolated)based on Region_Freeze 414 and hence, allowing these defined PR regionsto be reconfigured with the new configuration data. Accordingly, thedisabled PR regions will be skipped (e.g., not configured), withoutaffecting the operations of the disabled PR circuits. Generally, the IOreconfiguration can be achieved by shifting the new configuration datainto PR region 321A based on CLK 312 such that a shifted configurationdata signal is produced. The shifted configuration data signal may betransmitted to the corresponding IO block (controlled by the defined PRregion) to be reconfigured.

During CSR configuration, a selected output data signal (e.g., DOUT 419)of each PR region may be transmitted to the next PR region of theintegrated circuit (e.g., using multiplexer circuit 307) to facilitatethe PR region enabling operations of the next PR region. Accordingly,the global configuration control signals, CLK 312, and ESR controlsignals (e.g., Region_En Out 430 and Region_CE 317) are also transmittedto the next PR region for the same purpose.

FIG. 5 shows an illustrative bitstream format of configuration bitstream500 for the IO and peripheral CSR of an integrated circuit in accordancewith an embodiment of the present invention. Generally, integratedcircuits (e.g., integrated circuit 300 of FIG. 3) are configured byreceiving data from an electronic design automation tool. This data maybe referred to as a configuration bitstream, which may be included in aprogram object file (POF). The configuration bitstream may be loadedinto the configuration memory cells (e.g., memory elements 20 of FIG. 1)of the integrated circuit. The configuration of the integrated circuitis driven by the configuration bitstream from a configuration controller(e.g., control circuit 301 of FIG. 3).

Depending on user design requirements, the format and the content of theCSR configuration bitstream may be defined to implement different typesof configuration shift register (CSR) configurations on a singleintegrated circuit. For example, as shown in FIG. 5, the format ofconfiguration bitstream 500 for a full CSR configuration or a partialinitial CSR configuration may begin with a PR region enable data section(e.g., PR region enable data 501) that defines (e.g., enables) one ormore (an N number of) CSR partial reconfiguration regions (may bereferred to as PR regions herein) in a CSR chain (e.g., CSR chain 308 ofFIG. 3) to be configured.

It is then followed by a PR data section (e.g., PR data section 502)that includes PR data portions for configuring the defined PR regions.For example, PR data[1] may configure the first CSR PR region (e.g., PRregion 321A) in the CSR chain, PR data[2] may configure the second PRregion (e.g., PR region 321B) in the CSR chain, and PR data[N] mayconfigure the N-th PR region in the CSR chain.

Lastly, configuration bitstream 500 is concluded by an ending PR regiondisable data section (e.g., PR region disable data 503) to disable allthe defined PR regions. In one embodiment, PR region enable data 501 andPR region disable data 503 may be part of a CSR PR circuit enable data(e.g., Region_En_In 318 of FIG. 3) that is supplied to the integratedcircuit to facilitate individual CSR PR region enabling.

In some cases, specific CSR partial reconfiguration regions (which maybe referred to as PR regions herein) may be enabled for partial CSRconfiguration (or reconfiguration) to facilitate IO configuration of anintegrated circuit. FIG. 6 is an illustrative bitstream format ofconfiguration bitstream 600 for the integrated circuit, in accordancewith an embodiment of the present invention. It should be appreciatedthat FIGS. 3 and 6 may be used as examples to illustrate the followingdescription.

In one embodiment, only configuration data portions of the enabled PRregions may be included in configuration bitstream 600. As an example,in FIG. 3, CSR PR region 321B (will be referred to as PR region herein)may be enabled and PR region 321A may be disabled prior to performingeither initial partial CSR configuration or partial CSR reconfigurationin integrated circuit 300. In this scenario, the configuration dataportion for first PR region (e.g., PR region 321A) in CSR chain 308 isnot included in the configuration bitstream 600, which means that theconfiguration of PR region 321A will be skipped (e.g., not configured)during the partial CSR configuration operation.

Similar to configuration bitstream 500 of FIG. 5, the format ofconfiguration bitstream 600 for the initial partial CSR configuration orpartial CSR reconfiguration may begin with a CSR PR region enable datasection, followed by a PR data section, and concluded with an ending PRdisable section. In one embodiment, the data sections of configurationbitstream 600 may only contain information that enables the CSRconfiguration of the second PR region (e.g., PR region 321B). Forexample, PR region enable data 621 may include data bits that enableonly the second PR region, PR data section 602 may include data bitsthat configures the second PR region, and PR region disable data 623 mayinclude data bits that disables the second PR region after the operationof the partial CSR configuration or partial CSR reconfiguration iscompleted.

FIG. 7 is an illustrative timing diagram 700 showing the outputs of fulland initial partial CSR configuration of enabled PR regions 321A and321B of integrated circuit 300 of FIG. 3, in accordance with anembodiment of the present invention. It should be appreciated that thefull CSR configuration (or reconfiguration) and initial partial CSRconfiguration may share the same flow of operation and therefore, thetiming diagram for both circuit operations may be share similaritieswith each other.

In one embodiment, the IO configuration of an integrated circuit (e.g.,integrated circuit 300 of FIG. 3) is controlled by configuration databits of a configuration bitstream provided to the device for thatpurpose. In this example, a set of global configuration global signalsmay be provided to IO and periphery region 305 (by control circuit 301of FIG. 3) based on configuration bitstream 500 of FIG. 5. The set ofsignals, as shown in timing diagram 700, may include a global freezesignal (e.g., Global_Freeze 314), a PR circuit clock enable signal(e.g., Region_CE 317), a PR circuit enable data signal (e.g.,Region_En_In 318), a CSR clock enable signal (e.g., CSR_CE 315), a CSRdone signal (e.g., CSR_Done 316), and a CSR data input signal (e.g., DIN311). Region enable circuitry 351 and region control circuitry 352 ofFIG. 3 may generate a set of local region control signal, as shown intiming diagram 700, including a PR circuit enable control signal (e.g.,Region_En 411), a region clock enable control signal (e.g.,Region_CSR_CE 415), a region done control signal (e.g. Region_Done 416),and a region freeze control signal (e.g. Region_Freeze 414).Accordingly, a clock signal (e.g., CLK 312) from control circuit 301 ofFIG. 3 may be used to synchronize all the circuit operations in PRregions 321A and 321B of CSR chain 308. It should be appreciated thatall of the global signals from control circuit 301 may change on thefalling (or negative) edges of CLK 312 and all the registers in IOcircuitry 305 may be latched by the rising (or positive) edges of CLK312 to avoid potential timing conflicts.

When integrated circuit 300 is powered up, the elements within PRregions 321A and 321B in CSR chain 308 of FIG. 3 may reset to theirrespective initial states. For example, the binary values ofGlobal_Freeze 314, Region_CE 317, Region_En 411, and CSR_CE 315, arereset to “0”, respectively. Accordingly, the binary value of CSR_Done316 is reset to “1”, respectively. Correspondingly, the binary values ofthe local generated signals Region_CSR_CE 415, Region_Freeze 414, andRegion_Done 416 may be overridden to the binary values of CSR_CE 315(“0”), Global_Freeze 314 (“0”), and CSR_Done 316 (“1”), respectively.

During the full and initial partial CSR configuration operations, eachof PR regions 321A and 321B may perform specific region enablingoperations (which have been described previously in FIG. 4) based ondata bit information in configuration bitstream 500 of FIG. 5. Forexample, the region enabling operations performed by PR region 321A and321B during the time interval between T₁ and T₄ may be specified by PRcircuit enable data 501 of configuration bitstream 500. Accordingly, theregion enabling operations performed by PR region 321A and 321B duringthe time interval between T₄ and T₅ may be specified by PR data section502. Lastly, the region enabling operations performed by PR regions 321Aand 321B during the time interval between T₅ and T₈ may be specified byPR region disable data 503 of FIG. 5.

To simplify the following description, only the embodiments of PR region321A will be used to describe timing diagram 700, even though all otherPR regions (e.g., PR region 321B) within the same CSR chain (e.g., CSRchain 308) may be operating simultaneously. At the time interval betweenT₁ to T₇, Global_Freeze 314 is asserted (e.g., set to “1”) to PR region321A to globally isolate PR region 321A from core logic region 303 ofFIG. 3. In this embodiment, Region_Freeze 414 is overridden by theGlobal_Freeze 314 and therefore, the phase of Region_Freeze 414 is thesame as the phase of Global_Freeze 314.

At the time interval between T₂ to T₃, enable registers 420A and 420B ofregion enable circuitry 351 may be clocked by CLK 312 and PR circuitclock enable signal (e.g., Region_CE 317) of FIG. 4. For example, asshown in FIG. 4, enable register 420A may perform sequential bitshifting on enable shift register (ESR) data (e.g., Region_En_In 318) atevery rising edge of CLK 312 such that an output data signal (e.g.,reference output data 423) is shifted out from enable register 420A.

At the time T₃, Region_CE 317 is deasserted (e.g., set to “0”) and staydeasserted until time T₆. At this stage, the deasserted Region_CE 317may then be locally inverted by inverter 422 and applied to the clockenable port of shadow enable register 420B. Shadow enable register 420Bmay receive reference output data 423 from enable register 420A andperform sequential bit shifting on it to produce region enable circuitryoutput (e.g., Region_En 411). For example, as shown in timing diagram700, Region_En 411 is asserted once reference output data 423 of FIG. 4is shifted out from shadow enable register 420B by CLK 312. In oneembodiment, region control circuitry 352 may control PR region 321A bysending a control signal (e.g., Region_CSR_CE 415) that is indicative ofregion enabling operations, based on Region_En 411.

In order to activate a shifting operation in PR region 321A, CSR_CE 315is asserted and AND-ed together with Region_En 411 at logic gate 425 tobecome Region_CSR_CE 415. When Region_CSR_En 415 is received by PRregion 321A, the use of CLK 312 is enabled by Region_CSR_CE 415 toactivate a shifting operation in PR region 321A. In one embodiment,CSR_CE 315 is asserted to ensure that a data bit from DIN 311 is shiftedinto every one of the configuration registers (e.g., configurationregisters 435A, 435B, and 435C) in PR region 321A.

At the time interval between T₄ to T₅, once the last data bit of DIN 311is shifted in, each configuration register in PR region 321A produces ashifted data bit output to its corresponding logic gates (e.g., logicgate 436A, 436B and 436C). Accordingly, PR region 321A may also generatea shifted version of DIN 311 as an input to multiplexer circuit 307. Inone embodiment, multiplexer circuit 307 of FIG. 4 may be controlled byRegion_En 411 to select the shifted data signal output of DIN 311 whenPR region 321A is enabled for CSR configuration. Subsequently, theselected shifted data output from multiplexer circuit 307 is transmittedout from PR region 321A as DOUT 419 of FIG. 4.

At time T₅, CSR_CE 315 is deasserted to indicate that the shiftingoperation of DIN 311 in PR region 321A is complete. At this stage, PRregion 321A is disabled from shifting to prevent unwanted shiftingentry. Accordingly, CSR_Done 316 is asserted at the same time (e.g.,time T₅) to indicate that the CSR configuration is completed.Region_Done 416 is asserted in response to the assertion of CSR_Done 316to control logic gates 436A-436C to select the shifted data bit outputfrom their respective configuration register and transmit the selectedshifted data bit output to IO block 304A to be configured.

At the time interval between T₆ to T₇, Region_CE 317 is set to “1” againto enable the use of CLK 312 so that Region_En_In 318 can be shiftedthrough enable registers 420A and 420B.

At the time interval between T₇ to T₈, Region_CE 317 is deasserted againto apply a shifted output of Region_En_In 318 to PR region 321A. Such aconfiguration releases the region wide freeze to PR region 321A fromlogical isolation, in which PR region 321A was enabled previously inorder to facilitate the CSR configuration operations. Accordingly,Global_Freeze 314 is deasserted to release IO block 304A from thecontrol of PR region 321A.

FIG. 8 is an illustrative timing diagram 800 showing the outputs ofpartial CSR reconfiguration of an enabled PR region in an integratedcircuit in accordance with an embodiment of the present invention. Asmentioned above, the partial CSR reconfiguration can be initiated toachieve IO reconfiguration in the integrated circuit (e.g., integratedcircuit 300 of FIG. 3) during user mode. It should be appreciated thatFIGS. 3 and 6 may be used as examples to illustrate the followingdescription.

In an exemplary implementation, PR region 321B of FIG. 3 may be enabledand PR region 321A of FIG. 3 may be disabled in order to facilitate theIO reconfiguration during user mode. In this context, integrated circuit300 may receive a new configuration bitstream (e.g., configurationbitstream 600 of FIG. 6) containing the configuration data portion of PRregion 321B that configures PR region 321B.

As shown in timing diagram 800, the signals involved during the circuitoperations of the partial CSR reconfiguration is the same as thatpreviously described with respect to FIG. 7, except that theGlobal_Freeze 314 may always keep low. Therefore, it should beappreciated that for the sake of brevity, the global configurationcontrol signals and the local reconfiguration control signals alreadyshown in timing diagram 700 of FIG. 7 (e.g., clock signal CLK 312,Region_CE 317, Region_En 411, CSR_CE 315, CSR_Done 316, Region_CSR_CE415, and Region_Done 416) and described above will not be repeated.

As shown in the embodiment of timing diagram 800, due to Global_Freeze314 may be always low, Region_Freeze 414 now may be overridden byRegion_En 411 during region enabling operations of PR region 321B. Theassertion and deasssertion of Region_Freeze 414 may depend on Region_En411 to locally freeze (e.g., isolate) the enabled PR region 321B fromcore logic region 303 of FIG. 3. When Region_Freeze 414 is asserted(e.g., set to “1”) during the time interval between T₃ to T₈, both PRregion 321B and IO block 304B of FIG. 3 are logically isolated from eachother. Such a configuration allows PR region 321B to be reconfigured byPR circuit 302B. Accordingly, the new undefined (e.g., disabled) PRregion (e.g., PR region 321A) will be skipped, without affecting theoperations of existing disabled PR regions, if any. In this scenario,all the disabled PR regions will be gated (e.g., disconnected ordisabled) by CSR_Done 316.

FIG. 9 shows a flow chart of illustrative steps for reconfiguring aconfiguration shift register (CSR) partial reconfiguration region of anintegrated circuit in accordance with an embodiment of the presentinvention. In one embodiment, the steps shown in FIG. 9 may be performedby an electronic design automation (EDA) tool during compilation of theintegrated circuit or user design. It should be appreciated that FIGS. 3and 4 may be used as examples to describe the steps below.

At step 901, an input configuration data is received. The inputconfiguration data may be a configuration bitstream such asconfiguration bitstream 500 of FIG. 5 and configuration bitstream 600 ofFIG. 6. For example, the input configuration data may include CSR dataand partial reconfiguration (PR) circuit enable data that facilitate theCSR configuration of the integrated circuit.

At step 902, it is determined whether the PR circuit enable dataassociated with a configuration shift register PR region is present inthe input configuration data. In one embodiment, the configuration shiftregister PR region, or simply PR region, may be connected to a PRcircuit that facilitates the CSR configuration of the PR region.Referring to FIG. 3, the PR circuit (PR circuits 302A and 302B) mayinclude two components, namely region enable circuitry (e.g., regionenable circuitry 351) and region control circuitry (e.g., region enablecircuitry 352). The region enable circuitry enables the configuration ofthe PR region, and the region control circuitry controls theconfiguration of the PR region.

If PR region enable data is present in the input configuration data,local reconfiguration control signals are generated based on the PRcircuit enable data are generated at step 903. In an exemplaryembodiment shown in FIG. 4, when Region_En 411 is asserted by regionenable circuitry 351 to region control circuitry 352, region controlcircuitry 352 of PR circuit 302A may generate a set of localreconfiguration control signals (e.g., Region_CSR_CE 415, Region_Done416, Region_Freeze 414) to activate and facilitate the configurationoperations of PR region 321A at step 904.

In another embodiment, if the PR region enable signal is not present inthe input configuration, it means that the PR region is disabled frombeing configured and will be skipped at step 905. For example, the CSRdata (e.g., DIN 311 of FIG. 3) of the input configuration data willbypass the disabled PR region through a multiplexer circuit (e.g.,multiplexer circuit 307 of FIG. 3) without being written into the PRregion. The CSR data is subsequently transmitted to the next PR region(e.g., PR region 321B of FIG. 3) for the same purpose of enabling thereconfiguration of the next PR region.

The methods and apparatus described herein may be incorporated into anysuitable circuit. For example, the methods and apparatus may beincorporated into numerous types of devices such as microprocessors orother integrated circuits. Exemplary integrated circuits includeprogrammable array logic (PAL), programmable logic arrays (PLAs), fieldprogrammable logic arrays (FPGAs), electrically programmable logicdevices (EPLDs), electrically erasable programmable logic devices(EEPLDs), logic cell arrays (LCAs), field programmable gate arrays(FPGAs), application specific standard products (ASSPs), applicationspecific integrated circuits (ASICs), just to name a few.

The programmable logic device described herein may be part of a dataprocessing system that includes one or more of the following components;a processor; memory; IO circuitry; and peripheral devices. The dataprocessing system can be used in a wide variety of applications, such ascomputer networking, data networking, instrumentation, video processing,digital signal processing, or any suitable other application where theadvantage of using programmable or re-programmable logic is desirable.The programmable logic device can be used to perform a variety ofdifferent logic functions. For example, the programmable logic devicecan be configured as a processor or controller that works in cooperationwith a system processor. The programmable logic device may also be usedas an arbiter for arbitrating access to a shared resource in the dataprocessing system. In yet another example, the programmable logic devicecan be configured as an interface between a processor and one of theother components in the system. In one embodiment, the programmablelogic device may be one of the family of devices owned by the assignee.

Although the method operations were described in a specific order, itshould be understood that other operations may be performed in betweendescribed operations, described operations may be adjusted so that theyoccur at slightly different times or described operations may bedistributed in a system which allows the occurrence of the processingoperations at various intervals associated with the processing, as longas the processing of the overlay operations are performed in a desiredway.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention.

What is claimed is:
 1. An integrated circuit, comprising: aconfiguration shift register that includes a first partialreconfiguration region, a second partial reconfiguration region, a firstmultiplexer that receives signals from the first partial reconfigurationregion, and a second multiplexer that receives signals from the secondpartial reconfiguration region; a first partial reconfiguration circuitthat selectively enables the first partial reconfiguration region; and asecond partial reconfiguration circuit that selectively enables thesecond partial reconfiguration region.
 2. The integrated circuit ofclaim 1, wherein the first multiplexer is configured to selectivelybypass the first partial reconfiguration region, and wherein the secondmultiplexer is configured to selectively bypass the second partialreconfiguration region.
 3. The integrated circuit of claim 1, whereinthe first multiplexer is controlled by the first partial reconfigurationcircuit, and wherein the second multiplexer is controlled by the secondpartial reconfiguration circuit.
 4. The integrated circuit of claim 1,wherein the first partial reconfiguration circuit includes a regioncontrol circuit.
 5. The integrated circuit of claim 4, wherein theregion control circuit includes a plurality of logic gates that receivesglobal configuration control signals.
 6. The integrated circuit of claim5, further comprising: an input-output block, wherein the first partialreconfiguration region receives signals from the plurality of logicgates, and wherein the input-output block receives signals from both thefirst partial reconfiguration region and the plurality of logic gates.7. The integrated circuit of claim 4, wherein the first partialreconfiguration circuit further includes a region enable circuit thatoutputs signal to the region control circuit.
 8. The integrated circuitof claim 7, wherein the region enable circuit includes an enableregister and a shadow enable register that receives signals from theenable register.
 9. The integrated circuit of claim 7, wherein theregion enable circuit receives partial reconfiguration region enablecontrol signals.
 10. The integrated circuit of claim 1, wherein thefirst multiplexer is coupled between the first partial reconfigurationregion and the second partial reconfiguration region.
 11. A method ofoperating an integrated circuit that includes a configuration shiftregister, the method comprising: with a region control circuit,receiving global reconfiguration control signals and generatingcorresponding local reconfiguration control signals; and receiving thelocal reconfiguration control signals at the configuration shiftregister.
 12. The method of claim 11, wherein the integrated circuitfurther includes core logic circuitry and input-output blocks, andwherein receiving the global reconfiguration control signals comprisesreceiving a global freeze signal that, when asserted, isolates the corelogic circuitry from the input-output blocks.
 13. The method of claim12, wherein the global freeze signal is only asserted during a fullconfiguration shift register configuration operation that reconfiguresthe entire configuration shift register.
 14. The method of claim 12,wherein receiving the global reconfiguration control signals comprisesreceiving a done signal that indicates when reconfiguration of theconfiguration shift register is complete.
 15. The method of claim 12,wherein receiving the global reconfiguration control signals comprisesreceiving a clock enable signal that, when asserted, allows data to beshifted into the configuration shift register.
 16. A method of operatingan integrated circuit that includes a configuration shift register,comprising: with a region enable circuit, receiving an asserted globalfreeze control signal; and in response to receiving the asserted globalfreeze control signal, asserting a corresponding local freeze controlsignal to a given partial reconfiguration region within theconfiguration shift register.
 17. The method of claim 16, furthercomprising: performing a partial reconfiguration operation on the givenpartial reconfiguration region while the global freeze control signal isdeasserted.
 18. The method of claim 16, further comprising: with aregion enable register, simultaneously receiving an asserted clockenable signal and an asserted enable data signal.
 19. The method ofclaim 18, further comprising: with the region enable register,generating a region enable output signal; and latching the region enableoutput signal at a shadow enable register that is connected in serieswith the region enable register.
 20. The method of claim 19, furthercomprising: asserting the local freeze control signal in response todetermining that the shadow enable register has latched an assertedsignal.